1. Field of the Invention
The present invention relates generally to a parallel-to-serial readout circuitry, and more particularly to a parallel-to-serial readout circuitry that is part of a readout circuit of an image sensor.
2. Description of the Related Art
An image sensor generally includes a readout circuit of some form for reading out pixel signal values from pixels in a pixel array. One form of readout circuit includes multiple Analog to Digital Converters (ADCs) though which analog pixel signal values are read out in parallel and converted into digital form. For example, there may be one ADC provided for each column of the pixel array, and pixel signal values of one row of pixels at a time may be read out in parallel through the ADCs. The output of the ADCs (a series of bits making up digital pixel values) is then read out serially through some form of parallel-to-serial readout circuit. Because the serial readout of the digital pixel values takes a period of time, the parallel-to-serial readout circuit preferably should temporarily store the digital pixel values so that the ADCs can begin converting a next round of pixel signal values without having to wait until all of the previously converted values have been read out serially.
One form of the parallel-to-serial readout circuit used to read out the digital pixel values from the ADCs is a conventional shift register. For example, the output of each ADC may be an input of the shift register. The shift register stores the bits of the pixel values in the flip-flops making up the shift register, and shifts the bits once each clock cycle. The end bit in the register is output each clock cycle, and thus the bits of the digital pixel values are output serially over a number of clock cycles as they are “shifted out” of the register.
Another form of parallel-to-serial readout circuit uses a holding device (e.g., a sample-and-hold circuit) and a tri-state buffer for each bit output by an ADC. The bits of the digital pixel values output by the ADCs are temporarily held by their corresponding holding device, whose output is connected to one of the tri-state buffers. A bus is provided, and the tri-state buffers are controlled such that one buffer drives the bus per clock cycle based on the bit held in the holding device, thus serially reading out a signal on the bus that corresponds to the bits of the digital pixel values held in the holding devices.